The present invention generally relates to improvements in high aspect ratio etching and, in particular, relates to reverse masking profiling to provide a more uniform mask height between the array and periphery portions of a memory cell to mitigate twisting during high aspect ratio etching.
Today's semiconductor-based integrated circuits and micro-electro-mechanical systems (MEMS) are pushing the limits of many deep etch processes with their need for increasingly deeper and narrower contacts that have aspect ratios greater than 40:1. High aspect ratio (HAR) etching could be key in the future development of devices with high device/feature densities on a semiconductor wafer such as, for example, dynamic random access memory (DRAM) container capacitors and FLASH contacts.
However, as the aspect ratio of the plasma etch increases, twisting is increasingly becoming an issue. “Twisting” is the lateral offset of the bottom of an etched feature from the top. In a cross section, the twisted features bends in the X or Y direction, i.e., to the left and right of the page (X-direction) or in and out of the page (Y-direction). During plasma etching, as the aspect ratio increases, twisting becomes more common. The twisting is caused by asymmetric feature charging, which results in a lateral electrical field. In general, feature charging is due to the electrons having an isotropic velocity distribution, i.e., the thermal velocity is larger than the directed velocity, while the ions have an anisotropic velocity distribution, i.e., the directed velocity is much larger than the thermal velocity. For ions, the directed velocity is normal to the wafer, due to their acceleration by the plasma sheath. This means that most of the electrons will deposit their charge near the top of an HAR feature while the ions deposit their charge more toward the bottom. This results in the top of the feature charging negatively and the bottom positively. If this vertical charging becomes azimuthally asymmetric than the lateral electric field results, causing twisting. Asymmetric charging is caused by asymmetric mask geometry, which results in different view angles for electron and ion fluxes at different locations around the circumference of the contact or container. Differential electric charge builds up on the mask, causing local distortion of the ion trajectory at the edge of the array. This is often stochastic in the array, due to small variation in polymer deposition or lithographic induced asymmetries. At the edge of the array, systematic twisting is frequently observed, wherein the last several (up to 40) features twist in the direction of the edge of the array. One common, and problematic, example of twisting is in a DRAM container oxide etches. During oxide etching, twisting can result in “open” capacitors when the DRAM container does not land on the contact. Alternatively, twisting can cause shorts (doublebits) when two containers twist together.
Theory and computer simulation have shown that the twisting at the edge of the array is caused by different hard mask heights between the periphery and array portions of the semiconductor wafer. As described below, the different mask heights are caused by the faceting of the hard mask. The different mask heights result in a lateral electric field toward the periphery. This electric field pushes ions in the same direction. It is believed that this causes, or at least contributes, to the systematic twisting seen toward the moat at the edge of the array. In other words, for plasma etching with a strong ion energy component, i.e., the etch is as much or more physically driven than it is chemically driven, facets naturally develop because the peak angular yield of incident ions occurs at off-normal incidence. Typically, this is about 60 degrees. Oxide etch chemistries are typically done at high bias and the dominant ion is argon (Ar+). This means that the oxide etch ions are, in fact, quite physically driven, and prone to faceting.
In the array, the facets “come together” due to the small critical dimension of the space (the “line”) between the dynamic random access memory (DRAM) containers. In doing so, the etch rate of the mask in the array is naturally increased as compared to etch rate of the open, peripheral areas due to these geometric considerations. In addition, the difference in open area (i.e., the area to be etched) in the array versus the open area in the periphery contributes to a loading difference that tends to increase the mask loss in the array as compared to periphery. These two effects together result in less mask remaining in the array portion of the semiconductor wafer than in the periphery portion toward the end of a high aspect ratio etch. It is at the time that the systematic twisting typically occurs.
Therefore, it is important to reduce the relative height differential between array and periphery, which results in a lateral electric field and, therefore twisting. This could be done by reducing the faceting of the mask during high-aspect-ratio etches. However, the problem is overconstrained and the high bias and chemistries needed to drive an oxide etch at high aspect ratios results in a fairly fixed level of mask faceting and, therefore, result in a difference in mask height between the periphery and the array.
Therefore, there is a need to provide a solution to the problem of twisting at the edge of an array portion of a semiconductor wafer during high aspect ratio etching by reducing the difference in mask heights between the periphery and the array.